Verilog modules¶

Modules · Simulation · Waveforms

Write Verilog or SystemVerilog in RGate’s desktop source editor, run the module, and watch its signals. Combine source modules with schematic clocks, switches, DIP inputs, and LEDs to create an interactive circuit.

Try the PWM example¶

Download pwm-verilog.rgate and open it with File → Open….
Select pwm in Modules and choose Edit to see its source.
Return to main and click Play. The clock drives the dimmer instance.
Double-click DUTY and enter a hexadecimal byte: 40 for 25%, 80 for 50%, or C0 for 75% duty.
Probe pwm_out to see the pulse width in Waveforms.
Open the live dimmer instance and probe cnt to follow the counter.

RGate shows compilation progress while keeping the workspace responsive. Click Stop to cancel a compile.

Stop simulation, change the PWM expression, and run again to see your change. Source edits become part of the document as you type; File → Save keeps them in the .rgate file.

Open an existing source file¶

Choose File → Open… and select a .v or .sv file. RGate imports its module definitions and infers their ports. If the file has several definitions, choose the top module in the dialog. Select any definition in Modules to edit it. Save as .rgate to keep the source definitions with your schematic workspace.

Create a module¶

Choose Module → New Verilog module…. Give it a name that matches the source module declaration. The dialog provides a counter template; you can also paste source of your own.

For example, name the module counter and use:

module counter (
    input wire clk,
    input wire reset,
    input wire enable,
    output reg [7:0] count
);
    always @(posedge clk)
        if (reset)
            count <= 0;
        else if (enable)
            count <= count + 1;
endmodule

RGate reads input, output, and inout ports from the source, including packed bus widths and default parameter expressions. Click Apply to create the module. Edit source in the Edit tab; starting a run refreshes the inferred ports.

Open Ports… to see each pin’s direction and width. Edit port declarations in the source, then choose Refresh from source to update schematic instance pins. Keep connected widths consistent with the parent; disconnect affected pins before changing widths. Use Simulate → Browse HDL signals… to inspect internal signals and add probes during a run.

Connect it to a schematic¶

Switch to a schematic parent, such as main.
Find your module under Module instances in Components and place it.
Connect a Clock to clk, switches to reset and enable, and an eight-bit LED to count.
Start simulation. Assert reset=1 for a clock edge, then set reset=0 and enable=1.
Watch the counter advance. Pause or clock-step to inspect individual updates.

An instance uses the definition’s declared ports. Editing the definition updates its instances. Stop simulation before source edits; disconnect affected instances before changing connected port widths.

Run a module on its own¶

Select the source module and start simulation. Declared inputs begin at zero. Select an input in Nets, then choose Module → Set selected HDL input… and enter its value in hexadecimal.

For the counter above, set reset=1 and change clk from 0 to 1 to clear count. Set the clock back to 0, release reset, set enable=1, then raise the clock again. count becomes 1. A schematic Clock makes repeated cycles easier.

Inspect signals and diagnose source¶

Choose Simulate → Browse HDL signals… to explore live hierarchy. Filter by an instance path, click a signal to inspect its value, and choose Probe to record it without restarting simulation. Click ○ beside a declared signal to record it in Waveforms. Outputs and internal observations appear in Nets with their live values. Navigate to a specific schematic instance to inspect that copy while the simulation continues.

If a run reports an error, read Messages for the source location or signal name. Check the module declaration, interface names, and bus widths, correct the source, and run again. Run source you trust.

A .rgate document keeps your source, signal interface, schematic instances, and layout together. File → Export Verilog… exports the circuit and source modules for use in other Verilog tools.

Use desktop RGate for Verilog editing and execution. The browser app provides schematic editing and simulation, plus source viewing and editing through its source dialog.